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r10ds0148ej0200 rev.2.00 page 1 of 29 aug 01, 2014 datasheet r1qna4436rbg,r1qna4418rbg 144-mbit qdr?ii+ sram 2-word burst architecture (2.0 cycle read latency) description the r1qna4436rbg is a 4,194,304-word by 36-bit and the r1qna4418rbg is a 8,388,608-word by 18-bit synchronous quad data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. it integrates unique synchronous periphera l circuitry and a burst counter . all input registers are controlled by an input clock pair (k and /k) and are latche d on the positive edge of k and /k. these products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these produ cts are packaged in 165-pin plastic fbga package. features ? power supply z 1.8 v for core (v dd ), 1.4 v to v dd for i/o (v ddq ) ? clock z fast clock cycle time for high bandwidth z two input clocks (k and /k) for precise ddr timing at clock rising edges only z two output echo clocks (cq and /cq) simplify data capture in high-speed systems z clock-stop capability with s restart ? i/o z separate independent read and write data ports with concurrent transactions z 100% bus utilization ddr read and write operation z hstl i/o z user programmable output impedance z pll circuitry for wide output data valid window and future frequency scaling z data valid pin (qvld) to indicate valid data on the output ? function z two-tick burst for low ddr transaction size z internally self-timed write control z simple control logic for easy depth expansion z jtag 1149.1 compa tible test access port ? package z 165 fbga package (15 x 17 x 1.4 mm) r10ds0148ej0200 rev.2.00 aug 01, 2014
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 2 of 29 aug 01, 2014 part number definition column no. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 example r 1 q n a 4 4 3 6 r b g - 3 0 i b 0 the above part number is just example for 144m qdrii+ b2 x36 333mhz, 15x17mm pkg, pb-free part. no. - comments no. - comments no. - comments 0-1 r1 renesas memory prefix 4 a vdd = 1.8 v 60 frequency = 167mhz q2 qdr ii b2 [*1] (l15) [*2] 36 density = 36mb 50 frequency = 200mhz q3 qdr ii b4 (l15) 72 density = 72mb 40 frequency = 250mhz q4 ddr ii b2 (l15) 44 density = 144mb 36 frequency = 275mhz q5 ddr ii b4 (l15) 88 density = 288mb 33 frequency = 300mhz q6 ddr ii b2 sio [*3] (l15) 09 data width = 9bit 30 frequency = 333mhz qa qdr ii+ b4 l25 [*2] 18 data width = 18bit 27 frequency = 375mhz qb ddr ii+ b2 l25 36 data width = 36bit 25 frequency = 400mhz qc ddr ii+ b4 l25 r 1st generation 22 frequency = 450mhz qd qdr ii+ b4 l25 w/odt [*4] a 2nd generation 20 frequency = 500mhz qe ddr ii+ b2 l25 w/odt b 3rd generation 19 frequency = 533mhz qf ddr ii+ b4 l25 w/odt c 4th generation 18 frequency = 550mhz qg qdr ii+ b4 l20 d 5th generation qh ddr ii+ b2 l20 e 6th generation qj ddr ii+ b4 l20 f 7th generation qk qdr ii+ b4 l20 w/odt bg pkg= bga 15x17 mm ql ddr ii+ b2 l20 w/odt bb pkg= bga 13x15 mm a pb - and tray qm ddr ii+ b4 l20 w/odt b pb-free and tray qn qdr ii+ b2 l20 tpb - and tape&reel qp qdr ii+ b2 l20 w/odt s pb-free and tape&reel note1: [*1] b=burst length (b2: burst length=2, b4: burst length=4) [*2] l=read latency (l15: read latency = 1.5 cycle, l20: 2.0 cycle, l25: 2.5 cycle) [*3] sio=separate i/o [*4] odt=on die termination note2: package marking name pb - parts: marking name = part number(0-14) pb-free parts: marking name = part number(0-14) + "pb-f" (example) r1qaa4436rbg-20r pb-f ----- pb - parts (example) r1qaa4436rbg-20r pb-f ----- pb-free parts note3: pb -free : rohs compliance level = 5/6 pb-free: rohs compliance level = 6/6 note4: r1q*a series support both "commercial" and "industrial" temperatures by "industrial" temperature parts. - industrial temp. ta range = -40 to 85 i 15 0 to 9, a to z or none renesas internal use 10-11 --- r commercial temp. ta range = 0 to 70 12-13 14 2-3 5-6 7-8 9 - 16
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 3 of 29 aug 01, 2014 part number information ordering part number organization (word x bit) cycle time clock frequency operating ambient temperature core supply voltage (v) package r1qna4436rbg-30ia0 4m x 36 3.00ns 333mhz t a = ? 40 to 85c 1.8 0.1 165-pin r1qna4436rbg-33ia0 3.30ns 300mhz plastic r1qna4418rbg-30ia0 8m x 18 3.00ns 333mhz bga (15 x 17) r1qna4418rbg-33ia0 3.30ns 300mhz pb r1qna4436rbg-30ib0 4m x 36 3.00ns 333mhz t a = ? 40 to 85c 1.8 0.1 165-pin r1qna4436rbg-33ib0 3.30ns 300mhz plastic r1qna4418rbg-30ib0 8m x 18 3.00ns 333mhz bga (15 x 17) r1qna4418rbg-33ib0 3.30ns 300mhz pb-free
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 4 of 29 aug 01, 2014 pin arrangement [ r1qna4436rbg ] 4m x 36 (top view) 1 2 3 4 5 6 7 8 9 10 11 a /cq nc sa /w /bw2 /k /bw1 /r sa sa cq b q27 q18 d18 sa /bw3 k /bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h /doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa nc sa sa sa tms tdi notes: 1. address expansion order for future higher density srams: 10a 2a 7a 5b. 2. nc pins can be left floating or connected to 0v to v ddq
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 5 of 29 aug 01, 2014 [ r1qna4418rbg ] 8m x 18 (top view) 1 2 3 4 5 6 7 8 9 10 11 a /cq sa sa /w /bw1 /k nc /r sa sa cq b nc q9 d9 sa nc k /bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h /doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa nc sa sa sa tms tdi notes: 1. address expansion order for future higher density srams: 10a 2a 7a 5b. 2. nc pins can be left floating or connected to 0v to v dd q
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 6 of 29 aug 01, 2014 pin descriptions name i/o type descriptions note sa input synchronous address inputs: these i nputs are registered and must meet the setup and hold times around the rising edge of k (read address) and /k (write address). these inputs are ignored when device is deselected. /r input synchronous read: when low, this in put causes the address inputs to be registered and a read cycle to be initiated. this i nput must meet setup and hold times around the rising edge of k. /w input synchronous write: when low, this in put causes the address inputs to be registered and a write cycle to be initiated. this i nput must meet setup and hold times around the rising edge of k. /bw x input synchronous byte writes: when low, t hese inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and /k for each of the two rising edges comprising the write cycle. see byte write truth table for signal to data relationship. k, /k input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising e dge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain v ref level. /doff input pll disable: when low, this input causes the pll to be bypassed for stable, low frequency operation. tms tdi input ieee1149.1 test inputs: 1.8 v i/o levels . these balls may be left unconnected if the jtag function is not used in the circuit. tck input ieee1149.1 clock input: 1.8 v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2 rq, where rq is a resistor from this ball to gr ound. this ball can be connected directly to v ddq , which enables the minimum impedance mode. this ball cannot be connected directly to v ss or left unconnected.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 7 of 29 aug 01, 2014 name i/o type descriptions note d 0 to d n input synchronous data inputs: input dat a must meet setup and hold times around the rising edges of k and /k during write oper ations. see pin arrangement figures for ball site location of individual signals. the 18 device uses d0 to d17. d18 to d35 should be treated as nc pin. the 36 device uses d0 to d35. cq, /cq output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tri-states. tdo output ieee 1149.1 test output: 1.8 v i/o level. q 0 to q n output synchronous data output s: output data is synchronized to the k clock. this bus operates in response to /r commands. see pin arrangement figures for ball site location of individual signals. the 18 device uses q0 to q17. q18 to q35 should be treated as nc pin. the 36 device uses q0 to q35. qvld output valid output indicator: the q va lid indicates valid output data. qvld is edge aligned with cq and /cq. v dd supply power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. 1 v dd q supply power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operatin g conditions for range. 1 v ss supply power supply: ground. 1 v ref - hstl input reference voltage: nominally v ddq /2, but may be adjusted to improve system noise margin. provides a refer ence voltage for the hstl input buffers. nc - no connect: these pins can be left floating or connected to 0v to v dd q. notes: 1. all power supply and ground balls must be co nnected for proper oper ation of the device.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 8 of 29 aug 01, 2014 block diagram [r1qna4436rbg] [r1qna4418rbg] address /r /w k /k /w /bwx d (data in) /r k /k 72 72 21 36 36 q (data out) 21 k k,/k zq 2 cq /cq address registry and logic data registry and logic memory array e t i r w r e t s i g e r t u p t u o r e t s i g e r t u p t u o t c e l e s t u p t u o r e f f u b r e v i r d e t i r w p m a e s n e s x u m 72 4 k address /r /w k /k /w /bwx d (data in) /r k /k 36 /36 22 18 18 q (data out) 22 k k,/k zq 2 cq /cq address registry and logic data registry and logic memory array e t i r w r e t s i g e r t u p t u o r e t s i g e r t u p t u o t c e l e s t u p t u o r e f f u b r e v i r d e t i r w p m a e s n e s x u m 36 2 k
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 9 of 29 aug 01, 2014 status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff k, /k fix high (=vddq) power-up and initialization sequence v dd must be stable before k, /k clocks are applied. - recommended voltage application sequence : v ss v dd v ddq & v ref v in . (0 v to v dd , v ddq < 200 ms) - apply v ref after v ddq or at the same time as v ddq . - then execute either one of the following sequences. 1. single clock mode - drive /doff high (/doff can be tied high from the start). - then provide stable clocks (k, /k) for at least 20 us. 2. pll off mode (/doff tied low) - in the "nop and setup stage", provide stable clocks (k, /k) for at least 20 us. pll constraints 1. these chips use the pll. the clock input should have low phase jitter which is specified as tkc var. 2. the lower end of the frequency at wh ich the pll can operate is 250 mhz. (please refer to ac characteristics table for detail.) 3. when the operating frequency is changed or /doff level is changed, setup cycles are required again.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 10 of 29 aug 01, 2014 programmable output impedance 1. output buffer impedance can be programmed by terminating the zq ball to v ss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 and 350 . the total external capacitance of zq ball must be less than 7.5 pf. qvld (valid data indicator) 1. qvld is provided on the qdr-ii+ and ddr-ii+ to simplify data capture on high speed systems. the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for capturing the data. qvld is inactivated ha lf cycle before the read finish for th e receiver to stop capturing the data. qvld is edge aligned with cq and /cq.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 11 of 29 aug 01, 2014 k truth table operation k /r /w d or q write cycle: load address, input write data on two consecutive k and /k rising edges l data in input data d(a+0) d(a+1) input clock k(t) k(t) read cycle: load address, output read data on consecutive k and /k rising edges l data out output data q(a+0) q(a+1) input clock /c(t+2) /c(t+2) nop (no operation) h h d = x or q = high-z standby (clock stopped) stopped x x previous state notes: 1. h: high level, l: low level, : don?t care, : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at k clock edges. 3. /r and /w must meet setup/hold times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timi ng diagrams for clarification. 6. when clocks are stopped, the following cases are reco mmended; the case of k = low, /k = high, or the case of k = high, /k = low. this condition is not esse ntial, but permits most rapid restart by overcoming transmission line charging symmetrically.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 12 of 29 aug 01, 2014 byte write truth table ( x 36 ) operation k /k /bw0 /bw1 /bw2 /bw3 write d0 to d35 - l l l l - l l l l write d0 to d8 - l h h h - l h h h write d9 to d17 - h l h h - h l h h write d18 to d26 - h h l h - h h l h write d27 to d35 - h h h l - h h h l write nothing - h h h h - h h h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. byte write truth table ( x 18 ) operation k /k /bw0 /bw1 write d0 to d17 - l l - l l write d0 to d8 - l h - l h write d9 to d17 - h l - h l write nothing - h h - h h notes: 1. h: high level, l: low level, : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 13 of 29 aug 01, 2014 bus cycle state diagram notes: 1. the address is concatenated with one additional internal lsb to facilitate burst operation. the address order is always fixed as: xxx?xxx+0, xxx?xxx+1. bus cycle is terminated at the end of this sequence (burst count = 2). 2. read and write state machines can be active simultaneously. read and write cannot be simultaneously initiated. read takes precedence. 3. state machine control timing sequ ence is controlled by k. read port nop r init = 0 read double load new read address power up /r = h write port nop /w = h supply voltage provided supply voltage provided /r = l always /r = l /r = h write double at /k load new write address at /k /w = l always /w = l /w = h
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 14 of 29 aug 01, 2014 electrical characteristics absolute maximum ratings parameter symbol rating unit notes input voltage on any ball v in ? 0.5 to v dd + 0.5 (2.5 v max.) v 1,4 input/output voltage v i/o ? 0.5 to v ddq + 0.5 (2.5 v max.) v 1,4 core supply voltage v dd ? 0.5 to 2.5 v 1,4 output supply voltage v ddq ? 0.5 to v dd v 1,4 junction temperature tj +125 (max) c 5 storage temperature t stg ? 55 to +125 c notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute ma ximum ratings are exceeded. functional operation should be restricted the operation conditions. exposu re to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to m eet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.5 v, whatever the instantaneous value of v ddq . 5. some method of cooling or airflow should be considered in the system. recommended dc operating conditions parameter symbol min typ max unit notes power supply voltage -- core v dd 1.7 1.8 1.9 v 1 power supply voltage -- i/o v ddq 1.4 1.5 v dd v 1,2 input reference voltage -- i/o v ref 0.68 0.75 0.95 v 3 input high voltage v ih (dc) v ref + 0.1 - v ddq + 0.3 v 1,4,5 input low voltage v il (dc) -0.3 - v ref - 0.1 v 1,4,5 notes: 1. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time, v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . 2. please pay attention to tj not to exceed the temperature shown in the absolute maximum ratings table due to current from v ddq . 3. peak to peak ac com ponent superimposed on v ref may not exceed 5% of v ref . 4. these are dc test criteria. the ac v ih / v il levels are defined separately to measure timing parameters. 5. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh/ 2 during normal operation, v ih(dc) must not exceed v ddq and v il(dc) must not be lower than v ss.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 15 of 29 aug 01, 2014 dc characteristics (t a = -40 to +85 c, v dd = 1.8v 0.1v, v ddq = 1.5v, v ref = 0.75v) parameter symbol test condition min. max. uni t notes -30 -33 operating supply i dd (x36) 1230 1150 ma 1,2,3 current (x18) 980 920 (write / read) standby supply i sb1 (x36) 920 870 ma 2,4,5 current (x18) 800 750 (nop) input leakage current i li -2 2 output leakage current i lo -5 5 output high voltage v oh (low) |i oh | 0.1 ma v ddq ? 0.2 v ddq v 8 v oh note 6 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 8 output low voltage v ol (low) i ol 0.1 ma v ss 0.2 v 8 v ol note 7 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 8 notes: 1. all inputs (except zq, v ref ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max, t khkh = t khkh min. 3. operating supply currents (i dd ) are measured at 100% bus utilization. i dd of qdr family is current of device with 100% write and 100% read cycle. 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. reference value. (condition = nop currents are valid when entering nop after all pending read and write cycles are completed. ) 6. outputs are impedance-controlled. |i oh | = (v ddq /2)/(rq/5) for values of 17 5 rq 350 . 7. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 rq 350 . 8. ac load current is higher than the shown dc valu es. ac i/o curves are available upon request. 9. 0 v in v ddq for all input balls (except v ref , zq, tck, tms, tdi ball). 10. 0 v out v ddq (except tdo ball), output disabled.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 16 of 29 aug 01, 2014 thermal resistance parameter symbol airflow typ unit test condition notes junction to ambient ja 1 m/s 9.7 c/w eia/jedec jesd51 1 junction to case jc - 4.4 notes: 1. these parameters are calculated under the condition. these are reference values. 2. tj = ta + ja pd tj = tc + jc pd where tj : junction temperature when the device has achiev ed a steady-state after application of pd (c) ta :ambient temperature (c) tc :temperature of external surfa ce of the package or case (c) ja : thermal resistance from junction-to-ambient (c/w) jc : thermal resistance from junction-to-case (package) (c/w) pd :power dissipation that produced change in junction temperature (w) (cf.jesd51-2a) capacitance (t a = +25 c, frequency = 1.0mhz, v dd = 1.8v, v ddq = 1.5v) parameter symbol min typ max unit test condition note input capacitance (sa, /r, /w, /bw) c in - 4 5 pf v in = 0 v 1,2 clock input capacitance (k, /k) c clk - 4 5 pf v clk = 0 v 1,2 output capacitance (dq, cq, /cq) c i/o - 5 6 pf v i/o = 0 v 1,2 notes: 1. these parameters are sampled and not 100% tested. 2. except jtag (tck, tms, tdi, tdo) pins. ac test conditions input waveform (rise/fall time 0.3 ns) 1.25v 0.25v 0.75v 0.75v test points output waveform v ddq /2 test points v ddq /2
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 17 of 29 aug 01, 2014 output load conditions 50 zq q v ref 250 z 0 = 50 sram v ddq / 2 = 0.75v v ddq / 2 = 0.75v v dd v ddq v ss 1.8v0.1v 1.5v ac operating conditions parameter symbol min typ max unit notes input high voltage v ih (ac) v ref + 0.2 - - v 1,2,3,4 input low voltage v il (ac) - - v ref ? 0.2 v 1,2,3,4 notes: 1. all voltages referenced to v ss (gnd). during normal operation, v ddq must not exceed v dd . 2. these conditions are for ac functions only, not for ac parameter test. 3. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh /2 control input signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 4. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the curren t ac level through the target ac level, v il (ac) or v ih (ac) . b. reach at least the target ac level. c. after the ac target level is re ached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) .
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 18 of 29 aug 01, 2014 ac characteristics (t a = -40 to +85 c, v dd = 1.8v 0.1v, v ddq = 1.5v, v ref = 0.75v) parameter symbol -30 -33 unit notes min max min max clock average clock cycle time(k, /k) t khkh 3.00 4.00 3.30 4.00 ns clock high time (k, /k) t khkl 0.40 - 0.40 - cycle clock low time (k, /k) t klkh 0.40 - 0.40 - cycle clock to /clock (k to /k) t kh/kh 0.45 - 0.45 - cycle /clock to clock (/k to k) t /khkh 0.45 - 0.45 - cycle pll timing clock phase jitter (k, /k) t kc var - 0.20 - 0.20 ns 3 lock time (k) t kc lock 20 - 20 - us 2 k static to pll reset t kc reset 30 - 30 - ns 5 output times k, /k high to output valid t chqv - 0.45 - 0.45 ns k, /k high to output hold t chqx -0.45 - -0.45 - ns k, /k high to echo clock valid t chcqv - 0.45 - 0.45 ns k, /k high to echo clock hold t chcqx -0.45 -0.45 ns cq, /cq high to output valid t cqhqv - 0.20 - 0.20 ns 5 cq, /cq high to output hold t cqhqx -0.20 - -0.20 - ns 5 k, /k high to output high-z t chqz - 0.45 - 0.45 ns 4 k, /k high to output low-z t chqx1 -0.45 - -0.45 - ns 4 cq high to qvld valid t qvld -0.20 0.20 -0.20 0.20 ns 5 setup times address valid to k rising edge t avkh 0.28 - 0.30 - ns 1 control inputs valid to k rising edge t ivkh 0.28 - 0.30 - ns 1 data-in valid to k, /k rising edge t dvkh 0.28 - 0.30 - ns 1 hold times k rising edge to address hold t khax 0.28 - 0.30 - ns 1 k rising edge to control inputs hold t khix 0.28 - 0.30 - ns 1 k, /k rising edge to data-in hold t khdx 0.28 - 0.30 - ns 1
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 19 of 29 aug 01, 2014 notes: 1. this is a synchronous device. all addresses, data an d control lines must meet th e specified setup and hold times for all latching clock edges. 2. v dd and v ddq slew rate must be less than 0.1 v dc per 50 ns for pll lock retention. pll lock time begins once v dd , v ddq and input clock are stable. it is recommended that the device is kept inactive during these cycles. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. transitions are measured 100 mv from steady-state voltage. 5. these parameters are sampled. remarks: 1. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 2. control input signals may not be operated with pulse widths less than t khkl (min). 3. v ddq is +1.5 v dc. v ref is +0.75 v dc. 4. control signals are /r and /w. setup and hold times of /bwx signals must be the same as those of data-in signals.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 20 of 29 aug 01, 2014 read and write timing notes: 1. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 2. in this example, if address a2 = a1, then data q20 = d10, q21 = d11. write data is forwarded immediately as read results. 3. to control read and write operations, /bw signals must operate at the same timing as data-in signals. 1234567891011121314151617 k d10 d11 d30 d31 d50 d51 d70 d71 t khdx t dvkh t khdx t dvkh /k /r /w address data in t chqv -t chqx t chqv -t chqx t cqhqv -t cqhqx -t chqx1 q00 q01 q20 q21 q40 q41 q60 q61 t chqz t khkh t khkl t klkh t kh/kh t /khkh data out cq /cq a0 t khax t avkh t khix t ivkh read write nop nop read write read write nop write read write nop nop nop nop t khix t ivkh a2 a1 a4 a3 a5 a7 a6 a8 d80 d81 t qvld -t qvld t qvld -t qvld qvld t chcqv -t chcqx t chcqv -t chcqx
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 21 of 29 aug 01, 2014 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude middle level inputs. tdi and tms are internally pulled up and may be unconnected, or may be connected to vdd through a pull up resistor. tdo should be left unconnected. test access port (tap) pins notes: the device does not have trst (tap reset). the test-log ic reset state is entered while tms is held high for five rising edges of tck. the tap contro ller state is also reset on sram power-up. tap dc operating characteristics ( t a = -40 to +85 c, v dd = 1.8v 0.1v ) parameter symbol min typ max unit notes input high voltage v ih +1.3 - v dd + 0.3 v input low voltage v il -0.3 - +0.5 v input leakage current i li -5.0 - +5.0 v in v dd output leakage current i lo -5.0 - +5.0 a 0 v v in v dd , output disabled output low voltage v ol1 - - 0.2 v i olc = 100 a v ol2 - - 0.4 v i olt = 2 ma output high voltage v oh1 1.6 - - v |i ohc | = 100 a v oh2 1.4 - - v |i oht | = 2 ma notes: 1. all voltages referenced to v ss (gnd). 2. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time, v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . symbol i/o pin assignments description notes tck 2r test clock input. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the t ap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 22 of 29 aug 01, 2014 tap ac test conditions parameter symbol conditions unit notes input timing measurement reference levels v ref 0.9 v input pulse levels v il , v ih 0 to 1.8 v input rise/fall time tr, tf 1.0 ns output timing measurement reference levels 0.9 v test load termination supply voltage (v tt ) 0.9 v output load see figures input waveform 1.8v 0v 0.9v 0.9v test points output waveform 0.9v test points 0.9v output load condition external load at test 50 v tt = 0.9v tdo z 0 = 50 dut 20pf
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 23 of 29 aug 01, 2014 tap ac operating characteristics ( t a = -40 to +85 c, v dd = 1.8v 0.1v ) parameter symbol min typ max unit notes test clock (tck) cycle time t thth 50 - - ns tck high pulse width t thtl 20 - - ns tck low pulse width t tlth 20 - - ns test mode select (tms) setup t mvth 5 - - ns tms hold t thmx 5 - - ns capture setup t cs 5 - - ns capture hold t ch 5 - - ns tdi valid to tck high t dvth 5 - - ns tck high to tdi invalid t thdx 5 - - ns tck low to tdo unknown t tlqx 0 - - ns tck low to tdo valid t tlqv - - 10 ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 24 of 29 aug 01, 2014 tap controller timing diagram tck tdi tms tdo pi (sram) thtl thth tlth mvth thmx dvth thdx cs ch tlqv tlqx ttt tt t t t t tt test access port registers register name length symbol notes instruction register 3 bits ir [2:0] bypass register 1 bits bp id register 32 bits id [31:0] boundary scan register 109 bit bs [109:1]
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 25 of 29 aug 01, 2014 tap controller instruction set ir2 ir1 ir0 instruction description notes 0 0 0 extest the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply test vectors, whil e those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shift ed into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. 1,2,3,4 0 0 1 idcode the idcode instruction causes t he id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo balls in shift-dr mode. the idcode instruction is the defau lt instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. 0 1 0 sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z), moving the tap controller into the captur e-dr state loads the data in the rams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. 3,4 0 1 1 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 0 0 sample (/preload) when the sample instruction is load ed in the instruction register, moving the tap controller into t he capture-dr stat e loads the data in the rams input and i/o buffers in to the boundary scan register. because the ram clock(s) are in dependent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the ta p to sample metastable input will not harm the device, repeatable results cannot be expected. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo balls. 3,4 1 0 1 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 1 0 reserved the reserved instruction is not implemented but is reserved for future use. do not use this instruction. 1 1 1 bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be s hortened to facilitate testing of other devices in the scan path. notes: 1. data in output register is not guarant eed if extest instruction is loaded. 2. after performing extest, power-up conditions are required in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cycles are required after boundary scan.
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 26 of 29 aug 01, 2014 boundary scan order bit# ball id signal names bit# ball id signal names bit# ball id signal names x18 x36 x18 x36 x18 x36 1 6r nc nc 38 9e nc q15 75 2d d11 d20 2 6p qvld qvld 39 10c q7 q7 76 2e nc d29 3 6n sa sa 40 11d d7 d7 77 1e nc q29 4 7p sa sa 41 9c nc d16 78 2f q12 q21 5 7n sa sa 42 9d nc q16 79 3f d12 d21 6 7r sa sa 43 11b q8 q8 80 1g nc d30 7 8r sa sa 44 11c d8 d8 81 1f nc q30 8 8p sa sa 45 9b nc d17 82 3g q13 q22 9 9r sa sa 46 10b nc q17 83 2g d13 d22 10 11p q0 q0 47 11a cq cq 84 1h /doff /doff 11 10p d0 d0 48 10a sa sa 85 1j nc d31 12 10n nc d9 49 9a sa sa 86 2j nc q31 13 9p nc q9 50 8b sa sa 87 3k q14 q23 14 10m q1 q1 51 7c sa sa 88 3j d14 d23 15 11n d1 d1 52 6c sa sa 89 2k nc d32 16 9m nc d10 53 8a /r /r 90 1k nc q32 17 9n nc q10 54 7a nc /bw1 91 2l q15 q24 18 11l q2 q2 55 7b /bw0 /bw0 92 3l d15 d24 19 11m d2 d2 56 6b k k 93 1m nc d33 20 9l nc d11 57 6a /k /k 94 1l nc q33 21 10l nc q11 58 5b nc /bw3 95 3n q16 q25 22 11k q3 q3 59 5a /bw1 /bw2 96 3m d16 d25 23 10k d3 d3 60 4a /w /w 97 1n nc d34 24 9j nc d12 61 5c sa sa 98 2m nc q34 25 9k nc q12 62 4b sa sa 99 3p q17 q26 26 10j q4 q4 63 3a sa sa 100 2n d17 d26 27 11j d4 d4 64 2a sa nc 101 2p nc d35 28 11h zq zq 65 1a /cq /cq 102 1p nc q35 29 10g nc d13 66 2b q9 q18 103 3r sa sa 30 9g nc q13 67 3b d9 d18 104 4r sa sa 31 11f q5 q5 68 1c nc d27 105 4p sa sa 32 11g d5 d5 69 1b nc q27 106 5p sa sa 33 9f nc d14 70 3d q10 q19 107 5n sa sa 34 10f nc q14 71 3c d10 d19 108 5r sa sa 35 11e q6 q6 72 1d nc d28 109 - internal internal 36 10e d6 d6 73 2c nc q28 37 10d nc d15 74 3e q11 q20 notes: in boundary scan mode, 1. clock balls (k, /k) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are synchronized to the k clock (except extest, sample-z).
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 27 of 29 aug 01, 2014 id register V # 313029282726252423222120191817161514131211109876543210 symbol r r r 0 c m m m a w w 0 1 q q q b o s 0 0 1 0001000111 rrr q 000 0 001 1 010 q 011 0 1 cq 00 11 mmm b 0 1 0 density = 36mb 0 0 1 1 density = 72mb 1 1 0 1 density = 144mb o 1 1 0 density = 288mb 0 a1 0s 10 ww 1 00 10 11 36m&72m w/ odt 144m&288m w/o odt,36m,72m 144m&288m w/ odt x9 x18 x36 latency = 2.5(@ii+) burst latency = 2 word burst burst latency = 4 word burst without od t with odt common i/o separate i/o revision0 revision1 revision2 revision3 : : revision number (31:29) type number (28:12) ddr vendor jedec code (11:1) start bit(0) 36m&72m w/o odt,144m,288m ii(qdr-ii,ddr-ii) ii+(qdr-ii+,ddr-ii+) latency = 1.5(@ii).latency = 2.0(@ii+) qdr tap controller state diagram notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 1 1 0 0 11 test logic reset select ir scan capture dr shift dr exit1 dr pause dr exit2 dr update dr
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 28 of 29 aug 01, 2014 package dimensions and marking information reference symbol dimension in mm min nom max d 14.9 15.0 15.1 e 16.9 17.0 17.1 a--1.4 a1 0.31 0.36 0.41 [e] - 1.0 - b 0.45 0.5 0.6 x--0.2 y--0.15 z d - 2.5 - z e - 1.5 - -ys - ?x(m) s ab top view side view bottom view s a1 a z e z d r p n m l k j h g f e d c b a 1234567891011 [e] [e] ?b index mark a d index mark (laser mark) b e x x x x w w y f - b p n a p a j this part number or mark is just one example. marking information 1st row : vender name (r enesas ) 2nd row: part number 3rd row : y : year code ww : week code xxxx : renesas internal use 4th row : country name (japan) + "none" --- pb -free parts + "pb-f" --- pb-free parts both pb parts and pb-free parts are available. jeita package code renesas code previous code mass (typ.) p-lbga165-15x17-1.00 plbg0165fd-b r1qna4436rbg-30i r 1 q n a 4 4 3 6 r b g - 3 0 i 165fhe-b 0.6 g
r1qna4436rbg,r1qna4418rbg datasheet r10ds0148ej0200 rev.2.00 page 29 of 29 aug 01, 2014 revision history r1q na4436rbg,r1qna4418rbg rev. date description page summary rev.1.00 ?13.09.02 - new datasheet. rev.2.00 ?14.08.01 p15 modification : dc characteristics ,spec of i dd and i sb1 . qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, and renesas electronics corporation. http://www.qdrconsortium.org/ the information contained herein is subject to change without notice.
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